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discussion on electromagnetic compatibility of dsp
release time: 2018-05-01views: 430

1 introduction

since the first digital signal processor chip (dsp) came out in the early 1980s, dsp has brought great opportunities for the development of digital signal processing and a wide range of applications with the unique characteristics of digital devices, such as stability, repeatability, large-scale integration, especially programmability and easy to realize adaptive processing. however, because dsp is a quite complex, diverse digital and analog hybrid system with many subsystems, the interference of external electromagnetic radiation and the interference between internal components, subsystems and transmission channels on dsp and its data information has seriously threatened the stability, reliability and safety of its work [1]. according to statistics, dsp accidents caused by interference account for about 90% of its total accidents. at the same time, dsp inevitably radiates electromagnetic waves, which will interfere, hinder or damage human body and equipment in the environment. and with the improvement of dsp operation speed, the signal bandwidth that can be processed in real time is also greatly increased, and its research focus has also shifted to high-speed, real-time applications. but just like this, its electromagnetic compatibility is becoming more and more prominent. this paper discusses the electromagnetic compatibility of dsp.

2 electromagnetic compatibility of dsp hardware

electromagnetic compatibility (emc) includes the emission and sensitivity of the system. if interference cannot be completely eliminated, it should also be minimized. if a dsp system meets the following three conditions, the system is emc. (1) no interference to other systems; (2) insensitive to the emission of other systems; (3) there is no interference to the system itself.

2.1 main sources of interference in dsp

electromagnetic interference is generated through conductors or radiation. many electromagnetic emission sources, such as lighting, relays, dc motors and fluorescent lamps, can cause interference. ac power lines, interconnection cables, metal cables and internal circuits of subsystems may also generate radiation or receive unwanted signals. in high-speed digital circuits, clock circuits are usually the largest source of broadband noise. in the fast dsp system, these circuits can produce harmonic distortion signals up to 300mhz, which should be eliminated in the system. in digital circuits, reset lines, interrupt lines and control lines are the most vulnerable.

2.2 conductive interference in dsp

one of the most obvious propagation paths that can cause circuit noise is through conductors. a wire passing through the noisy environment can pick up the noise and send it to another circuit to cause interference. the designer must avoid wire picking up noise. if the noise enters the circuit through the power line, if the power supply itself or other circuits connected to the power supply are interference sources, it must be decoupled before the power line enters the circuit.

2.3 common impedance coupling in dsp

common impedance coupling occurs when current from two different circuits flows through a common impedance. the voltage drop across the impedance is determined by two circuits. the ground current from the two circuits flows through the common ground impedance, the ground potential of circuit 1 is modulated by ground current 2, and the noise signal or dc compensation is coupled from circuit 2 to circuit 1 through the common ground impedance.

2.4 radiation coupling in dsp

the coupling produced by radiation is commonly known as crosstalk. crosstalk is caused by the electromagnetic field generated when the current flows through the conductor, which will induce a transient current in the adjacent conductor.

2.5 radiation phenomenon in dsp

there are two basic types of radiation: differential (dm) and common mode (cm) modes. common mode radiation or monopole antenna radiation is caused by unintentional voltage drop, which raises all ground connections in the circuit above the system ground potential. in terms of the size of the electric field, cm radiation is a more serious problem than dm radiation. in order to minimize cm radiation, a practical design must be used to reduce the common mode current to zero.

2.6 factors affecting emc

(1) voltage: the higher the power supply voltage, the greater the voltage amplitude and the more emissions, while the lower the power supply voltage affects the sensitivity.

(2) frequency: high frequency signals and periodic signals will produce more radiation. in the high frequency digital system, when the device is in the switching state, the current spike signal will be generated; in the analog system, when the load current changes, the current spike signal will also be generated.

(3) grounding: in circuit design, nothing is more important than using a reliable and perfect grounding connection. in all emc problems, most of them are caused by improper grounding. there are three signal grounding methods: single point, multi-point and mixed. single point grounding method can be adopted when the frequency is lower than 1mhz; in high-frequency applications, it is best to use multi-point grounding; hybrid grounding is a combination of single point grounding at low frequency and multi-point grounding at high frequency. however, the ground circuit of high-frequency digital circuit and low-level analog circuit must not be mixed.

(4) pcb design: proper printed circuit board (pcb) wiring is very important to prevent electromagnetic interference.

(5) power decoupling: when the device is switched, transient currents will be generated on the power line, which must be attenuated and filtered. the transient currents from high di /dt sources cause the “emission” voltage of the ground and trace. high d i/dt generates a wide range of high-frequency current, which excites the radiation of components and cables. the change of current and inductance flowing through the wire will lead to voltage drop. reducing the change of inductance or current with time can minimize the voltage drop.

2.7 dsp hardware noise reduction technology

2.7.1 noise reduction technology in board structure and line arrangement

(1) adopt ground and power supply panel;

(2) the plate area should be large to provide low impedance for power decoupling;

(3) minimize surface conductors;

(4) narrow lines (4 to 8 mils) are used to increase high-frequency damping and reduce capacitive coupling;

(5) separate the ground / power lines of digital, analog, receiver and transmitter;

(6) separate circuits on pcb according to frequency and type;

(7) do not cut the pcb. the traces near the cut may lead to unwanted loops;

(8) the use of laminated structure is the best preventive measure against most signal integrity problems and emc problems. it can effectively control the impedance, and its internal wiring can form an easy to understand and predictable transmission line structure. and the traces between the power supply and the floor shall be sealed;

(9) keep the spacing between adjacent excitation traces larger than the width of traces to minimize crosstalk;

(10) the area of clock signal loop should be as small as possible;

(11) the high-speed line and clock signal line should be short and directly connected;

(12) sensitive traces should not be parallel to those transmitting high current fast switching conversion signals;

(13) do not have floating digital input to prevent unnecessary switching and noise generation;

(14) avoid power supply traces under crystal oscillator and other inherent noise circuits;

(15) the corresponding power, ground, signal and loop traces should be parallel to the scenery to eliminate noise;

(16) separate the clock line, bus and chip enabling end from the input / output line and connector;

(17) make the route clock signal and i/o signal in orthogonal position;

(18) in order to minimize crosstalk, the traces are crossed at right angles and scattered ground wires;

(19) protect the key traces (use 4-8 mil traces to minimize the inductance, the route is close to the floor, the interlayer structure between the floors, and there is ground on each side of the protective interlayer).

2.7.2 noise reduction method using filtering technology

(1) filter the power line and all signals entering the pcb, and use high-frequency low inductance ceramic capacitors (0.1 mf for 14mhz and 0.01mf for more than 15mhz) at each point pin of the ic for decoupling; (2) bypass all power supply and reference voltage pins of analog circuit;

(3) bypass fast switching device;

(4) decouple the power / ground at the device lead;

(5) multilevel filtering is used to attenuate multi band power supply noise;

(6) install and embed the crystal oscillator on the board and ground it;

(7) shield at appropriate places;

(8) arrange the adjacent ground wire close to the signal line, so as to more effectively prevent the emergence of new electric fields;

(9) place the decoupling line driver and receiver properly close to the actual i/o interface, which can reduce the coupling between pcb and other circuits, and reduce the radiation and sensitivity;

(10) shield and twist the interfering leads together to eliminate the mutual coupling on the pcb;

(11) clamp diode on inductive load

software interference is mainly manifested in the following aspects:

(1) the main reason for incorrect algorithm to produce wrong results is that the program index operation in the computer processor is approximate calculation, and sometimes the results have large errors, which is easy to produce misoperation;

(2) because the accuracy of the computer is not high, and the addition and subtraction operation needs to be in the right order, the large number “eats” the decimal, resulting in error accumulation, leading to the emergence of underflow, which is also one of the sources of noise;

(3) the computer caused by hardware interference, such as: program counter pc value changes, data acquisition error increases, control state failure, ram data changes due to interference, and the system appears “deadlock” and other phenomena.

3.1 method of intercepting out of control procedure

(1) single byte instructions should be used more in program design, and some empty operation instructions should be inserted at the key points, or the effective single byte instructions should be repeated several times, so as to protect the subsequent instructions from being disassembled and make the program run on the right track; (2) adding software traps: when the pc value is out of control and the program is out of control, the cpu enters the non program area. at this time, a boot instruction can be used to force the program into the initial entry state and enter the program area. a trap can be set every other section; (3) software reset: when the program “flies”, run the monitoring system to automatically reset and reinitialize the system.

3.2 judgment of setting signs

define a unit as a flag, set the value of the unit as a characteristic value in the module main program, and then judge whether the value of the unit remains unchanged at the end of the main program. if it is different, it indicates an error, and the program will turn to the error handling subroutine.

3.3 add data security backup

important data is stored in more than two storage areas, and large capacity external ram can also be used to back up the data. permanent data is made into tables and solidified in eprom, which can not only prevent data and tables from being destroyed, but also ensure that data will not be run as instructions when the program logic is chaotic.

4. several key factors that should be paid attention to when using eda tool design

on the one hand, the design of high-speed digital circuits needs the experience of designers, on the other hand, it needs the support of excellent eda tools. eda software has moved towards multi-function and intelligence. with the application of high-density single chip, high-density connector, micropore built-in technology and 3d board in the design of printed circuit board, layout and wiring have become more and more integrated, and become an important part of the design process. software technology such as automatic layout and free angle wiring has gradually become an important method to solve this kind of highly integrated problem. using this kind of software can design a manufacturable circuit board within a specified time range. at present, due to the shorter and shorter time to market of products, manual wiring is extremely time-consuming and cannot meet the requirements. therefore, the layout and routing tool is now required to have automatic routing function to quickly respond to the higher requirements of the market for product design.

4.1 automatic wiring technology

due to the consideration of high-density design factors such as electromagnetic compatibility (emc), electromagnetic interference, crosstalk, signal delay and differential pair wiring, the constraints of layout and wiring are increasing every year. a few years ago, the general circuit board needed only 6 differential pairs for wiring, but now it needs 600 pairs. it is impossible to only rely on manual wiring to realize these 600 pairs of wiring within a certain period of time, so automatic wiring tools are essential. although the number of nodes (net) in today’s design has not changed significantly compared with a few years ago, but the complexity of silicon wafer has increased, the proportion of important nodes in the design has greatly increased. of course, for some particularly important nodes, the layout and routing tool is required to distinguish, but there is no need to limit each pin or node.

4.2 methods that should be paid attention to when using free angle wiring technology

with the increase of integrated functions on single-chip devices, the number of output pins has also greatly increased, but its package size has not been expanded. in addition, due to the limitations of pin spacing and impedance factors, such devices must adopt thinner linewidth. at the same time, the overall reduction of product size means that the space for layout and wiring is also greatly reduced. in some dsp products, the size of the backplane is almost the same as that of the devices on it, and the components occupy as much as 80% of the board area. the pins of some high-density components are staggered, and even the tools with 45 ° wiring function cannot be used for automatic wiring. the free angle wiring tool has great flexibility, which can maximize the wiring density; its pull-tight function makes each node shorten automatically after wiring to meet the space requirements; it can greatly reduce the signal delay and the number of parallel paths, which helps to avoid crosstalk. using free angle wiring technology can make the design manufacturable, and the designed circuit performance is good.

4.3 technology to be adopted for high-density devices

the latest high-density system level chips are packaged in bga or cob, and the pin spacing is decreasing day by day. the ball spacing has been as low as 1mm, and will continue to decrease. this makes it impossible to use traditional wiring tools to lead out the signal wire of the package. at present, there are two methods to solve this problem: (1) through the hole under the ball, the signal line is led out from the lower layer; (2) a lead channel is found in the ball grid array by using extremely thin wiring and free angle wiring. for high-density devices, it is the only feasible way to use the wiring method with minimal width and space, because only in this way can we ensure a high yield. modern cabling technology also requires the automatic application of these constraints. the free wiring method can reduce the number of wiring layers and reduce the product cost. at the same time, it also means that some ground layers and power layers can be added to improve signal integrity and emc performance at the same cost.

4.4 adopt other new circuit board design and manufacturing technologies

the application of microporous plasma etching technology in the fabrication of multilayer board in dsp greatly improves the performance of layout and wiring tools. adding a new hole in the path width by plasma etching will not increase the base plate itself and the manufacturing cost, because the cost of making 1000 holes by plasma etching is as low as that of making one hole. this requires the wiring tool to have greater flexibility. it must be able to apply different constraints to meet the requirements of different micropores and construction technologies. the increasing density of components also has an impact on the layout design. the layout and wiring tools always assume that there is enough space on the board for the component release machine to release the surface, so that new components can be installed without affecting the existing components on the board. however, the sequential placement of components will cause such a problem that the best position of each component on the board will change every time a new component is placed. this is the reason for the low degree of automation and high degree of human intervention in the layout design process. although the current layout tools have no limit on the number of elements to be laid out in sequence, some technicians believe that the layout tools are actually limited when used for sequential layout, which is about 500 components. some technicians also think that when the yuan is placed on a board

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